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Quad, IEEE 802.3at/af PSE Controller
for Power-over-Ethernet
Port Voltage Registers (R32h, R33h, R36h, R37h,
R3Ah, R3Bh, R3Eh, and R3Fh)
The Port Voltage registers (Tables 34 and 35) provide
port voltage readout when a port is powered on. On
a power-up or after a reset condition, these registers
are both set to a default value of 00h. The Port Voltage
Readout registers have 16 total bits, but the 2 highest
bits (MSBs) and the 5 lowest bits (LSBs) are hardwired
to 0. The port voltage readout has 9 bits of overall actual
resolution. To avoid the LSB register changing while
Table 34. Port Voltage Register (LSB)
ADDRESS = 32h, 36h, 3Ah, 3Eh
SYMBOL BIT NO. TYPE
reading the MSB, the register contents are frozen if
addressing byte points to either of the Voltage Readout
registers. During normal operation, the port output volt-
age can be calculated as:
V OUT_ = N VP_ x 5.835mV/count
where N VP_ is the decimal value of the 16-bit port volt-
age readout. The ADC saturates both at full scale and at
zero, resulting in poor voltage readout accuracy near the
top and bottom codes.
DESCRIPTION
7
6
5
R
R
R
VP_[7:0]
4
3
2
1
0
R
R
R
R
R
VP_[7:0] (LSB). Lower 8 bits of the 16-bit port current readout. VP_[4:0] are config-
ured to be hardwired to 0.
Table 35. Port Voltage Register (MSB)
ADDRESS = 33h, 37h, 3Bh, 3Fh
SYMBOL BIT NO. TYPE
DESCRIPTION
7
6
5
R
R
R
VP_[15:8]
4
3
2
1
0
R
R
R
R
R
VP_[15:8] (LSB). Lower 8 bits of the 16-bit port current readout. VP_[15:13] are con-
figured to be hardwired to 0.
43
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